1. Field of the Invention
The present invention relates to a semiconductor device and an error correction method of data thereof, and more particularly, to a semiconductor memory device having an improved error correction circuit, and an error correction method for reducing circuit complexity of an error correction circuit.
2. Description of the Background Art
Some semiconductor memory devices have an error correction circuit (abbreviated as ECC hereinafter) incorporated for error correction of an erroneous data read out from a memory cell array.
The detection of whether there is an error in data of an arbitrary bit length is carried out by appending one bit of data called a parity bit to the data. This method of detection is called parity check. In parity check, the data of a parity bit is set so that the number of bits of ones is even (or odd) of the data to be checked and data of parity bit. Detection of an error of 1 bit is allowed by checking the number of bits of ones.
However, it is not possible to correct an error with parity check since the bit with an error cannot be identified. For the purpose of detecting an error and making a correction, data of a plurality of bits is appended to the data from which an error is to be detected. This data of a plurality of bits is called check bits, which are redundant bits for detection and correction of an error. Check bit data is called parity data hereinafter. Data having check bit appended is called an error correction code.
In general, a parity data of 6 bits and a parity data of 4 bits are required to be appended in correcting a single bit error occurring in data of 32 bits and 8 bits, respectively.
ECC carries out predetermined operation with the read out data and the corresponding parity bit for correcting the error in the read out data to provide eventually as the read out data a corrected data.
Such an ECC is adopted into a mask ROM (Read Only Memory) that has data previously written therein during manufacturing where only data read out is possible thereafter. The application of such ECC in EEPROMs (Electorically Erasable and Programmable ROM) for memory devices that can have data rewritten after manufacturing is proposed in U.S. patent application Ser. No. 4,958,352.
FIG. 10 is a block diagram schematically showing an example of a structure of a conventional mask ROM having an ECC. The structure of a conventional mask ROM having an ECC will be described hereinafter with reference to FIG. 10.
The mask ROM comprises a memory cell array 1 storing original data to be read out to an external source (referred to as a regular memory cell array hereinafter), and a memory cell array 2 storing parity bit for correcting the error in the data read out from memory cell array 1 (referred to as parity memory cell array hereinafter).
Memory cell array 1 comprises 32 blocks of DB0-DB31 corresponding to data of 32 bits. Similarly, parity memory cell array 2 comprises six blocks DP0-DP5 corresponding to a parity data of 6 bits.
A plurality of word lines WL are commonly provided for memory cell array 1 and parity memory cell array 2. A plurality of bit lines BL are provided for each of the 38 blocks of DB0-DB31 and DP0-DP5.
Word lines WL are connected to an X decoder 3. Bit lines B1 are connected to a Y gate 7. An address buffer 5 applies waveform shaping and amplification to an externally applied address signal via address input terminals A0-An to provide the same to X decoder 3 and Y decoder 4. X decoder 3 decodes the address signal from address buffer 5 to activate one of the plurality of word lines WL corresponding to that address signal.
Y decoder decodes the address signal from address buffer 5 to control Y gate 7.
More specifically, Y gate 7 is divided into 32 blocks of YGD0-YGD31 corresponding to the 32 regular memory cell array blocks DB0-DB31, and six blocks of YGP0-YGP5 corresponding to the six parity memory cell array blocks DP0-DP5. Each of the 32 blocks of YGD0-YGD31 in Y gate 7 responds to the decoded output of Y decoder 4 to electrically connect to a sense amplifier group 8 one of the plurality of bit lines of the corresponding regular memory cell array block. Similarly, each of the six blocks YGP0-YGP5 in Y gate 7 responds to the decoded output of Y decoder 4 to electrically connect to sense amplifier group 8 one of the plurality of bit lines BL of the corresponding parity memory cell array block.
Sense amplifier group 8 comprises 32 sense amplifiers SAD0-SAD31 and six sense amplifiers SAP0-SAP5 corresponding to the 32 Y gate blocks YGD0-YGD31 and the 6 Y gate blocks YGP0-YGP5, respectively. Each of the 38 sense amplifiers of SAD0-SAD31 and SAP0-SAP5 senses and amplifies the signal on the one bit line BL electrically connected by a corresponding Y gate block to provide the same to ECC 9.
Each of regular memory cell array blocks DB0-DB31 and parity memory cell array blocks DP0-DP5 comprises a memory cell MC arranged in a matrix of a plurality of rows and columns. Memory cells MC arranged in one row are connected to the same word line WL. Memory cells MC arranged in one column are connected to the same bit line BL.
The activation of one word line WL causes a signal according to the stored data in each memory cell MC connected to that word line WL to appear on the bit line BL connected to that memory cell MC. If there are N columns of the memory cell columns included in each regular memory cell array blocks of DB0-DB31 and each parity memory cell array blocks of DP0-DP5, the stored data of (38.times.N) memory cells MC connected to the same word line WL are simultaneously provided to Y gate 7.
Each of Y gate blocks YGD0-YGD31 provided corresponding to regular memory cell array 1 electrically connects only one bit line BL in the corresponding regular memory cell array block to a corresponding sense amplifier. Similarly, each of Y gate blocks YGP0-YGP5 provided corresponding to parity memory cell array 2 connects only one bit line BL of the corresponding parity memory cell array block to a corresponding sense amplifier. Therefore, sense amplifier group 8 amplifies one of the N data signals provided from memory cell array block DB0 to Y gate block YGD0, one of the N data signals provided from memory cell array block DB1 to Y gate block YGD1, . . . , one of the N data signals provided from memory cell array block DB31 to Y gate block YGD31, one of the N data signals provided from parity memory cell array block DP0 to Y gate block YGP0, . . . , and one of the N data signals provided from parity memory cell array block DP5 to Y gate block YGP5, to provide the same as an input signal of d0, d1, . . . , d31, P0, . . . , P5, respectively, to ECC 9.
Thus, the stored data of 38 memory cells MC connected to the same word line are read out to ECC 9 from respective ones of regular memory cell array blocks DB0-DB31 and parity memory cell array blocks DP0-DP5.
A predetermined parity data is written in parity memory cell array 2 at the time of manufacturing in order to generate, by the arithmetic operation of ECC 9 detection and correction of 1 bit error generated in the 38 bits of data d0-d31 and P0-P5 read out simultaneously from regular memory cell array 1 and parity memory cell array 2 to ECC 9. The parity data to be written in parity memory cell array 2 is determined according to the stored data of memory cell array 1.
The data to be read out to an external source is previously written into memory cell array 1 at the time of manufacturing. However, for various reasons, there are some cases where the data read out from memory cell array 1 is not the proper data. In such a case, the data read out from memory cell array 1 is corrected to the proper data by the operation of ECC 9.
ECC 9 is provided simultaneously with 32 bits of data d0-d31 to be read out to an external source, and 6 bits of parity data P0-P5 required to correct an error of one bit generated in the 32 bits of data. ECC 9 carries out predetermined operation with the 32 bits of data d0-d31 and 6 bits of parity data P0-P5 to provide a 32-bit data to output buffer 10. If there is no error, the 32-bit data is directly provided to output buffer 10. If there is an error in one of the 32 bits of data d0-d31 read out, the erroneous bit is corrected, whereby the 32-bit data is provided to output buffer 10.
In the present invention, ECC 9 selectively provides to output buffer 10 the less significant 16 bits of data d0-d15 and the more significant 16 bits of data d16-d31 of the error corrected 32 bits of data d0-d31.
Output buffer 10 amplifies the output signals of ECC 9, i.e. the corrected 16 bits of data d0-d15 (or d16-d31) to provide the same to data output terminals DT0-DT15.
Output buffer 10 comprises 16 buffer circuits of OUT0-OUT15 corresponding to the 16 bits of data provided from ECC 9. The 16 buffer circuits of OUT0-OUT15 are connected to the 16 data output terminals of DT0-DT15.
Control circuit 6 responds to an externally supplied control signal from control signal input terminal CTL to control the operation such as of address buffer 5 and output buffer 10.
FIG. 11 is a block diagram schematically showing the internal structure of ECC 9 of FIG. 10.
Before the description of the structure of ECC 9 is given, the arithmetic procedure and error correction mechanism of ECC 9 will be briefly described with reference to FIG. 11. The details of error correction and circuit thereof are provided in "Interface", Aug. 1984, pp. 236-250.
An error correction code y of m bits for detecting and correcting an error of 1 bit is represented as: EQU y=(y0 y1. . . y(m-1)) (1)
where y0, y1, . . . , y (m-1) are the logic values of the least significant bit, the second least significant bit, . . . the most significant bit of the error correction code.
Similarly, an error correction code having no erroneous bit, i.e. an expected data x of the m-bit data is represented as: EQU x=(x0 x1 . . . x (m-1)) (2)
where x0, x1, . . . , x (m-1) represent the proper logic values of the least significant bit, the second least significant bit, . . . , the most significant bit of the error correction code.
The indication of difference between respective bits of logic values of y0-y (m-1) of the error correction code and corresponding expected data of x0-x (m-1) is represented by the following matrix e (referred to as an error matrix hereinafter), where y=x+e holds. EQU e=(e0 e1 . . . e (m-1)) (3)
where e0, e1, . . . , e (m-1) represent the logic values of the offset of the least significant bit y0, the second least significant bit y1, . . . the most significant bit y (m-1) from corresponding expected data of x0, x1, . . . x (m-1), respectively. It is assumed that a logic value of 0 designates that there is no offset from the expected value and a logic value of 1 designates that there is an offset from the expected data. In the following equations, the operators of+in a circle and X represent addition and multiplication, respectively, with 2 as a modulus.
By the relationship of y=x+e, the relationship between the logic value yj of an arbitrary bit of the error correction code and the expected data thereof xj (j=0, 1, . . . (m-1)) is represented by the following equation: EQU yj=xj.sym.ej (4)
FIG. 20 is the truth table of modulo 2 addition. It can be appreciated from FIG. 20 that if the value B to be added is 0, the added result coincides with value A to which value B is added. If the value to be added B is 1, the added result indicates a logic value opposite that of value A to which value B is to be added.
Therefore, if the logic values of e0-e (m-1) are known, the expected values of x0-x (m-1) of each bit can be determined.
The presence of any error bit in error correction code x can be detected by using a matrix of elements of 1 and 0 which is called a Hamming matrix. Hamming matrix H is a matrix satisfying the relationship of the following equation: EQU H.multidot.x=0 (5)
If the logic values y0-y (m-1) of respective bits of not-yet-corrected correction error code y match the expected value x0-x (m-1), the relationship of H.multidot.x=0 holds. If the logic value of any bit in the error correction code y differs from the corresponding expected value thereof, H.multidot.y.noteq.0. The product H.y of Hamming matrix H and row y representing an error correction code prior to being corrected is called syndrome matrix S.
Syndrome matrix S indicates which bit of error correction code y has a logic value different from the expected value.
Syndrome matrix S can be obtained as below using a transpose H.sup.T of parity check matrix H, in accordance with the relationship among row y representing an error correction code prior to correction, expected data row x, and error matrix e. EQU e=H.sup.T .multidot.S (6)
It is understood from the above-described equation (4) that logic value yj of an arbitrary bit of error correction code y does not have to be corrected if identical to expected value xj. On the contrary, if logic value yj of an arbitrary bit differs from expected value xj thereof, logic value yj of that bit must be inverted. An error matrix is obtained by equation (6), and the proper logic value xj of an arbitrary bit of the error correction code can be obtained by: EQU xj=yj.sym.j (7)
By using a predetermined Hamming matrix H, one erroneous bit generated in the error correction code of an arbitrary bit length can be corrected.
When the error correction code is constituted by the original data of m.sub.1 bit length to be corrected, and parity data of m.sub.2 bit length, Hamming matrix H is a matrix of m.sub.2 rows and m.sub.1 columns, as shown in FIG. 22. FIG. 22 shows a typical form of a Hamming matrix.
Detection and correction of a bit error in a 32-bit data necessiates the addition of a 6-bit parity data to the 32-bit data. The operation for correcting an error of 1 bit generated in data of 32 bits will be described hereinafter.
The error correction code of 32-bit data d0-d31 and 6-bit parity data P0-P5 is represented by the following sequence DP: EQU DP=(d0 d1 . . . d31 P0 P1 . . . P5)
A Hamming matrix H of 6 rows.times.38 columns is determined according to the proper logic values of each bit of d0-d31, P0-P5 of the error correction code. In the following description, the element of the i-th row and the j-th column in Hamming matrix H is represented as h (i, j). Hamming matrix H is represented as follows: ##EQU1## where (i=0, 1, 2 . . . 5; j=0, 1, 2 . . . 37). Elements S0-S5 of syndrome matrix S are obtained the following calculation according to sequence DP corresponding to the error correction code and Hamming matrix H. ##EQU2## It can be appreciated from equation (8) that an arbitrary element Si of syndrome matrix S is obtained by the following calculation according to the i-th elements of h (i, 0)-h (i, 37) of Hamming matrix H and logic values of d0-d31 and P0-P5 of the relative bits of the error correction code. EQU Sj=d0.times.h (i,0).sym.d1.times.h (i,1) . . . .sym.d31.times.h (i,31) .sym.P0.times.h (i,32) . . . .sym.P5.times.h (i,37).
FIG. 21 is a truth table of modulo 2 multiplication It can be appreciated from FIG. 21 that the multiplication result (A.times.B) becomes 0 if the value B to be multiplied by is 0 regardless of multiplicand A. If value B to be multiplied by is 1, the multiplication result (A.times.B) attains a logic value identical to multiplicand A.
The i-th element Si of syndrome matrix S is obtained by adding, modulo 2, all the data of the error correction code which are to be multiplied, modulo 2, by the elements that are 1 in elements h (i, 0)-h (i, 37) of the i-th row of Hamming matrix H. Elements e0-e37 of error matrix e are calculated by the following expression in accordance with transpose H.sup.T of Hamming matrix H and elements S0-S5 of the calculated syndrome matrix. ##EQU3##
It can be appreciated from equation (9) that an arbitrary element ej of error matrix e is expressed as follows: EQU ej=h (0,j.times.S0 .sym.h (1,j).times.S1 .sym. - - - .sym.h (5, j).times.S5
The j-th element ej of error matrix e can be obtained by carrying out, modulo 2, multiplication with the elements of syndrome matrix S which should be multiplied by the elements which are 1 out of elements h (0,j)-h (5,j) in the j-th column of Hamming matrix H, and the opposite logic values of the elements of syndrome matrix S which should be multiplied by elements which are 0 of the elements in the j-th column.
Eventually, elements D0-D31 of the proper error correction code DP can be obtained by the following expression according to data d0-d31 and P0-P5 of each bit of the error correction code, and elements e0-e31 of the calculated error vector e. ##EQU4##
The calculated elements of D0-D31 are respectively the expected data of the respective bits of the data to be read out to an external source.
Thus, ECC 9 of FIG. 10 detects and corrects one bit error occurring in the data of 32 bits which are to be provided to an external source. The circuit configuration of ECC 9 will be explained with reference to FIG. 11. In the logic circuit, the high level potential and the low level potential correspond to logic values of 1 and 0, respectively.
A syndrome signal generator 90 generates 6 bits of syndrome signals S0-S5 and respective inverted signals corresponding to the aforementioned syndrome signals by carrying out an operation according to a predetermined Hamming matrix H for the 32 bits of data d0-d31 and the 6 bits of parity data P0-P5 read out from regular memory cell array 1 and parity memory cell array 2, respectively, of FIG. 10.
Specifically, an arbitrary syndrome signal Sj is obtained by carrying out an operation equal to that expressed in (8) with logic circuitry in syndrome signal generator 90.
A correction signal generator 91 generates 32 bits of correction signals e0-e31 corresponding to elements e0-e31 of the above-described error matrix e by carrying out operation according to the predetermined Hamming matrix for all the twelve bits of signals of the 6 bits of syndrome signals S0-S5 and the respective inverted signals generated from syndrome Signal generator 90.
Specifically, an arbitrary correction signal ej is obtained by executing an operation equal to that represented by (9) with logic circuitry in correction signal generator 91.
FIG. 12 is an example of a conventional Hamming matrix used for detecting and correcting an error of 1 bit generated in a 32-bit data. Syndrome signal generator 90 and correction signal generator 91 are implemented according to Hamming matrix H.
In the operation of obtaining syndrome signals, the respective bits of data in the error correction code correspond to the respective elements of each row of Hamming matrix H (refer to expression (8)).
In the operation of obtaining correction signals, each of the correction signals corresponds to the respective column of Hamming matrix H, and the respective bits of data of the syndrome signal correspond to the respective elements of each columns of Hamming matrix H (refer to equation (9)).
In the event of using Hamming matrix H indicated in FIG. 12, syndrome signal S0, for example, is calculated by adding, modulo 2, the 16 data of d10-d17, d25-d31 and P0 which correspond to the 16 elements which are 1 in the elements in the first row of Hamming matrix H. Similarly, syndrome signal S1 is obtained by adding, modulo 2, all the 16 data of d11-d25 and P1 which correspond to the 16 elements which are 1 in the elements in the second row of Hamming matrix H. In the same manner, each of syndrome signals S2-S5 is obtained by adding, modulo 2, all the 16 data corresponding to the elements which are 1 in the respective third to sixth rows of Hamming matrix H.
For example, syndrome signal S0 is obtained by the following operation: EQU S0=d10 .sym.d11 .sym. . . . .sym.d17 .sym.d25 .sym.d26 .sym. . . . d31 .sym.P0
The modulo 2 addition is equivalent to exclusive 0R in logical operation. Therefore, syndrome signal S0 is obtained by taking exclusive OR for all the sixteen data of d10-d17, d25-d31 and P0.
Similarly, each of the other five syndrome signals S1-S5 can be obtained by taking exclusive OR for the 16 data corresponding to the elements which are 1 in the elements in the corresponding row of Hamming matrix H.
Syndrome signal generator 90 includes a plurality of EX-OR gates. FIG. 13 is a circuit diagram showing a structure of syndrome signal generator 90 where the Hamming matrix H of FIG. 12 is used.
Referring to FIG. 13, syndrome signal generator 90 comprises six circuit blocks 90-1 to 90-6 generating syndrome signals of S0-S5, respectively.
Each of circuit blocks 90-1 to 90-6 comprises eight 2-input EX-OR gates 900a, four 2-input EX-OR gates 900b for receiving as an input the outputs of two EX-OR gates of the eight EX-OR gates 900a, two 2-input EX-OR gates 900c for receiving as an input the outputs of two EX-0R gates of the four EX-OR gates 900b, and a 2-input EX-0R gate 900d for receiving as an input the outputs of the two EX-OR gates 900c.
Each of circuit blocks 90-1 to 90-6 is supplied with 16 data of the 38 data of d0-d31 and P0-P5, which are required for calculating syndrome signals S0-S5.
FIG. 14 is a table showing the 16 input signals of I1-I16 to each of circuit blocks 90-1 to 90-6.
It can be understood from FIG. 14 that the input signals of I1-I16 to the respective circuit blocks of 90-1, 90-2, . . . , 90-6, are the 16 data corresponding to the elements of the first row, of the second row, . . . of the sixth row of Hamming matrix H which are 1, respectively. Therefore, the output signals from each EX-OR gate 900d in respective circuit blocks 90-1 to 90-6 are the six syndrome signals of S0-S5.
Each of circuit blocks 90-1 to 90-6 further comprises an inverter 900e for inverting the output of EX-OR gate 900d. Therefore, inverted signals of the six syndrome signals of S0-S5 are provided from inverter 900e in each of respective circuit blocks 90-1 to 90-6.
Each of correction signals e0-e31 are obtained by multiplying, modulo 2, the syndrome signals corresponding to the elements in the corresponding column of Hamming matrix H which are 1 by the inverted signals of the syndrome signals corresponding to the elements which are 0.
In the case the Hamming matrix H of FIG. 12 is employed, correction signal e0 for example, is obtained, modulo n, by multiplying two syndrome signals S4 and S5 corresponding to the elements which are 1 in the elements of the first column of Hamming matrix H by the four inverted signals of syndrome signals S0-S4 corresponding to the elements which are 0. That is to say, correction signal e0 is calculated by carrying out the following operation. EQU e0=/S0.times./S1.times./S2.times./S3.times.S4.times.S5
where/S0-/S3 represent the inverted signals of syndrome signals S0-S3, respectively.
The modulo 2 multiplication is equivalent to logical product in logical operation. Therefore, each of the 32 correction signals of e0-e31 is obtained by taking the logical product of all the 6 signals of the syndrome signals corresponding to the elements which are 1 and the inverted signals of the syndrome signals corresponding to the elements which are 0 of the elements of the corresponding columns of Hamming matrix H.
Accordingly, correction signal generator 91 comprises 32 circuit blocks which carry out an operation equivalent to that of an AND gate.
FIG. 15 is a circuit diagram showing an example of a structure of correction signal generator 91 where the Hamming matrix of FIG. 12 is employed.
Referring to FIG. 15, correction signal generator 91 comprises circuit blocks 91-1 to 91-32 for generating correction signals e0-e31, respectively.
Each of the 32 circuit blocks of 91-1 to 91-32 comprises two 3-input NAND gates 910a, and a 2-input NOR gate 910b for receiving as inputs the outputs of the two NAND gates 910a.
FIG. 16 is a table showing the six input signals i1-i6 provided to each of circuit blocks of 91-1 to 91-32. As shown in FIG. 16, NAND gate 910a of circuit block 91-1, NAND gate 910a of circuit block 91-2, . . . , NAND gate 910a of circuit block 91-32 are provided with the total of six signals of the syndrome signals corresponding to the elements which are 1 and the inverted signals of the syndrome signals corresponding to the elements that are 0 in the first column of Hamming matrix H, the total of 6 signals of the syndrome signals corresponding to the elements that are 1 and the inverted signals of the syndrome signals corresponding to the elements that are 0 in the second column of Hamming matrix H, . . . , the total of 6 signals of the syndrome signals corresponding to the elements that are 1 and the inverted signals of the syndrome signals corresponding to the elements that are 0 in the 32nd column of Hamming matrix H.
In each of circuit blocks of 91-1 to 91-32 forming correction signal generator 91, the output potential of NOR gate 910b attains a high logic level only when the output potentials of the two NAND gates 910a are both at a low level. The output potentials of the two NAND gates 910a both attain a low level only when the six input signals i1-i6 to these NAND gates 910a are all at a high level. In other words, the circuit implemented with two NAND gates 910a and one NOR gate 910b carries out an operation equivalent to that of a 6-input NAND gate.
Thus, correction signals e0, e1, . . . , e31 are provided from the NOR gate 910b of circuit block 91-1, circuit block 91-2, . . . , circuit block 91-32, respectively.
Referring to FIG. 11 again, data correction circuit 92 carries out the operation of (10) for correction signals e0-e31 generated from correction signal generator 91 and the 32 bits of data d0-d31 from regular memory cell array 1. FIG. 17 is a circuit diagram showing the structure of data correction circuit 92 where the Hamming matrix of FIG. 12 is shown.
Referring to FIG. 17, data correction circuit 92 comprises 32 2-input EX-OR gates 920.
EX-OR gates 92-1, 92-2 . . ., 92-32 are provided with correction signal e0 and data signal d0, correction signal e1 and data signal d1, . . . , correction signal e31 and data signal d31, respectively. Therefore, the output terminals of the 32 EX-OR gates 92-1, 92-2 . . ., 92-32 show the exclusive OR signal of signals e0 and d0, the exclusive 0R signal of signals e1 and d1, . . . , the exclusive OR signal of signals e31 and d31.
The 32 data signals d0-d31 appear at the output terminals of the respective EX-OR gates 92-1 to 92-32 inverted when differing from the corresponding expected values, and not inverted when matching the corresponding expected value. Thus, 32 bits of data signals d0-d31 with an error, if any, corrected, are provided as the proper data D0-D31 from the 32 EX-OR gates 92-1 to 92-32.
Referring to FIG. 11 again, a data selector 93 is controlled by a select signal SE to select and provide the 16 bits of signals D0-D15 or the other 16 bits of signals D16-D31 from data correction circuit 92.
FIG. 18 is a circuit diagram showing a structure of data selector 93.
Referring to FIG. 18, data selector 93 comprises sixteen circuit blocks 93-1 to 93-16. Each of circuit blocks 93-1 to 93-16 comprises two P channel MOS transistors 930a and 930c, and two N channel MOS transistors 930b and 930d. Transistors 930a and 930b are connected in parallel. Similarly, transistors 930c and transistor 930d are connected in parallel.
The transistors 930a and 930b of circuit block 93-1, circuit block 93-2, . . . , circuit block 93-16 are provided as the transfer gates of corrected data signals D0, D1, . . . , D15.
Similarly, the transistors 930c and 930d of circuit block 93-1, circuit block 93-2, . . . , circuit block 93-16 are provided as the transfer gates of the corrected data signals D16, D17, . . . , D31.
Select signal SE and an inverted signal thereof are provided to the gates of transistors 930b and 930c, and to the gates of transistors 930a and 930d.
A high level potential of select signal SE causes transistors 930a and 930b to attain a conductive state, and transistors 930c and 930d to a non-conductive state. Thus, the less significant 16 bits of data signals D0-D15 of the corrected 32 bits of data signals D0-D31 are provided from the 16 circuit blocks 93-1 to 93-16. On the contrary, the low level potential of select signal SE causes transistors 930c and 930d to attain a conductive state, and transistors 930a and 930b to attain a non-conductive state. Therefore, the more significant 16 bits of data signals D16-D31 are provided from the 16 circuit blocks 93-1 to 93-16.
FIG. 19 is a table showing the relationship between the potential logic levels of select signal SE and the inverted signal thereof, and output signals of O.sub.0 -O.sub.15 of data selector 93.
By switching the logic level of select signal SE, the data signals of the 16 bits of lower significance or the 16 bits of higher significance can be selectively provided. Select signal SE and the inverted signal thereof are generated from control circuit 6 of FIG. 10, for example.
As described above, a conventional ECC comprises a syndrome signal generator formed of a plurality of circuit blocks identical in number with the number of parity data simultaneously read out from a memory cell array, and a correction signal generator and a data correction circuit each formed of a plurality of blocks that are identical in number with the number of data excluding parity data read out.
Each of the plurality of circuit blocks forming the syndrome signal generator requires many input signal lines and includes many logical gate circuits. The circuit complexity of the syndrome signal generator is great.
Each of the plurality of circuit blocks forming correction signal generator and data correction circuit do not require as many input signal lines as for each of the plurality of circuit blocks forming the syndrome signal generator. However, the number of circuit blocks forming the correction signal generator and the number of circuit blocks forming the data correction circuit are significantly greater than those forming the syndrome signal generator. Therefore, the circuit complexity of the correction signal generator and the data correction circuit is great.
Thus, the occupying area of an ECC on the semiconductor substrate was great in a conventional semiconductor memory device having an ECC, leading to the problem that the area on the semiconductor substrate for the memory cell array is reduced.
In the case of the mask ROM of FIG. 10, for example, ECC 9 comprises 6 circuit blocks 90-1 to 90-6, each requiring 16 input signal lines and 15 EX-OR gates (refer to FIG. 13); 32 circuit blocks 91-1 to 91-32, each requiring 6 input signal lines, 2 NAND gates, and one NOR gate (refer to FIG. 15); and 32 EX-OR gates 92-1 to 92-32, each requiring 2 input signal lines.
Therefore, a conventional semiconductor memory device with an error correction function had a problem that it was difficult to increase memory capacity without increasing the chip size.